1. Technical Field
Embodiments may generally relate to a circuit portion for low dropout regulators. More particularly, but not exclusively, the embodiments may relate to a circuit portion coupled to a voltage regulator allowing such a regulator to enhance its speed and recovery from a voltage drop on its output. The disclosure may report a possible application for voltage regulators in memory devices with the only purpose of simplifying a description.
2. Related Art
As it is well known in this specific technical field, a low-dropout or LDO regulator is a direct current DC linear voltage regulator which can regulate the output voltage even when its supply voltage is very close to the output voltage. The advantages of a low dropout voltage regulator over other DC to DC regulators include a lower switching noise, a smaller device size, and greater design simplicity, etc.
Inside memory devices there are many voltage regulators, each one provided for a specific regulation purpose. Those regulators are however employed in many other electronic devices wherein a voltage output must be regulated with a certain precision and stability.
FIG. 1 schematically illustrates a circuit diagram of a conventional LDO regulator. The LDO regulator 100 comprises a comparator 10, a PMOS power transistor PM, connected to the output of the comparator 10, a first resistor R1 and a second resistor R2 serially connected between the output of the regulator and a ground voltage reference VSSI. The comparator 10 receives a reference voltage VCCI_REF at its positive input (+) and a feedback voltage FEED at its inverting input (−) and outputs an output voltage DVRP. The feedback voltage FEED is a voltage at a node A between the first resistor R1 and the second resistor R2. The gate of the PMOS transistor PM is coupled with the output terminal of the comparator 10. The source of the PMOS transistor PM is coupled to the power voltage PWR. The drain of the PMOS transistor PM is coupled with one terminal of the first resistor R1 and represents the output node OUT of the regulator 100 to be coupled to a load.
As can be appreciated by the previous description, the conventional LDO regulator 100 adopts a negative feedback network to stabilize the output voltage VOUT.
FIG. 2 illustrates a schematic view of a typical working scheme of a LDO regulator used in a memory device, for instance to regulate the programming voltage of the memory cells; the memory matrix is schematically indicated like a current generator G1 connected in parallel to a filter capacitance C1 having a relative high value. When reading or programming the memory cells a high amount of current is suddenly discharged to the load and an important voltage drop is generated in the output voltage VOUT at the output node OUT of the voltage regulator, as illustrated in FIG. 3. The vertical axis represents voltage levels of the output voltage VOUT (i.e., V1, V2, and V3,) and t represents time for the horizontal axis. The voltage drop is variable according for instance to the distance of the memory cell to be programmed from the terminals of the corresponding bit line and word line so that the resistive load to reach each cell is different.
So, a main voltage drop is due to the current peak requested for the programming phase while a reduced voltage drop is still present during a reading phase as illustrated in FIG. 3 by the dotted curve.
The drop of the output voltage VOUT causes a corresponding drop of the feedback voltage FEED that becomes smaller thus reducing the gain of the comparator and reducing the output voltage DVRP that controls the gate terminal of the power PMOS transistor PM. Therefore, the feedback voltage FEED is the method used by the known prior art solution to solve the problem of the fast recovery of the voltage output in LDO regulators. Late recovery Δt of the regulator's output voltage may cause a critical malfunction to the memory device.
However, the negative feedback network used to stabilize the output voltage VOUT would require also a power PMOS transistor PM having a great width/length W/L ratio to feed the required current peak. A big power transistor as an output driver involves a larger circuit area, higher costs and a higher consumption. Moreover, a big power transistor is associated to a compensation capacitance C2 between the gate and drain terminals and this reduces the recovery speed of the whole regulator if the compensation capacitance shall be designed with a certain high dimension and area consumption.
On the contrary, a sudden drop of the output voltage VOUT should be recovered as fast as possible because the memory devices of cutting edge technology operate in a quite high bandwidth.
Therefore, the standard LDO regulators require a long time response to recover a voltage drop on their outputs and if this time response must be shortened then the LDO must be structured for a higher consumption or a possible compensation of the parasitic capacitance effects.